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AL440C Data Sheet
Version 1.0
www..com
AVERLOGIC TECHNOLOGIES, INC. TEL: 1 408 361-0400 www..com
e-mail: sales@averlogic.com
URL: www.averlogic.com January 30, 2004
AL440C
Amendments
08-04-04 Change "Operating Current"; "Supply Voltage" to (3.16~3.6V).
AL440C
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AL440C
AL440C 4MBits FIFO Field Memory
Contents:
1.0 Description _________________________________________________________________ 4 2.0 Features____________________________________________________________________ 4 3.0 Applications_________________________________________________________________ 4 4.0 Ordering Information _________________________________________________________ 4
4.1 Marking Information _____________________________________________________________________ 5
5.0 Pin-out Diagram _____________________________________________________________ 5 6.0 Block Diagram ______________________________________________________________ 6 7.0 Pin Definition and Description _________________________________________________ 6 8.0 Multiple Devices Bus Expansion ________________________________________________ 8 9.0 Memory Operation ___________________________________________________________ 9
9.1 Power-On-Reset & Initialization ____________________________________________________________ 9 9.2 WRST, RRST Reset Operation _____________________________________________________________ 9 9.3 Control Signals Polarity Select _____________________________________________________________ 9 9.4 FIFO Write Operation ____________________________________________________________________ 9 9.5 FIFO Read Operation____________________________________________________________________ 10
10.0 Electrical Characteristics ____________________________________________________ 12
10.1 Absolute Maximum Ratings _____________________________________________________________ 12 10.2 Recommended Operating Conditions ______________________________________________________ 12 10.3 DC Characteristics _____________________________________________________________________ 12 10.4 AC Characteristics _____________________________________________________________________ 13
11.0 Timing Diagrams __________________________________________________________ 15 12.0 Mechanical Drawing - 44 PIN PLASTIC TSOP (II) ______________________________ 23 13.0 Application Notes __________________________________________________________ 25
13.1 Chip Global Reset Recommend Circuit_____________________________________________________ 25 13.2 The AL440C Reference Schematic ________________________________________________________ 25
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AL440C
1.0 Description
The AL440C 4Mbits (512k x 8-bit) FIFO memory provides completely independent 8bit input and output ports that can operate at a maximum speed of 80 MHz. The built-in address and pointer control circuits provide a very easy-to-use memory interface that greatly reduces design time and effort. Manufactured using state-of-the-art embedded high density memory cell array, the AL440C uses high performance process technologies with extended controller functions (write mask, read skip.. etc.), allowing easy operation of non-linearity and regional read/write FIFO for PIP, Digital TV, security system and video camera applications. Expanding AL440C data bus width is possible by using multiple AL440C chips in parallel. To get better design flexibility, the polarities of the AL440C control signals are selectable. The read and write control signals, such as Read/Write Enable, Input/Output Enable.., can be either active low or high by pulling /PLRTY signal to high or low respectively. Available as a 44-pin TSOP (II), the small footprint allows product designers to keep real estate to a minimum.
2.0 Features
* * * * * * * * 4Mbits (512k x 8 bits) organization FIFO Independent 8bit read/write port operations (different read/write data rates acceptable) Maximum Read/write cycle time: 80Mhz and 50Mhz (2 speed grades) Input Enable (write mask) / Output Enable (data skipping) control Selectable control signal polarity Self refresh 3.3V 10% power supply Standard 44-pin TSOP (II) package
3.0 Applications
* * * * * * * * * Multimedia systems Video capture or editing systems for NTSC/PAL or SVGA resolution Security systems Scan rate converters TBC (Time Base Correction) Frame synchronizer Digital video camera Hard disk cache memory Buffer for communication systems
* 80MHz High-Speed version * DTV/HDTV video stream buffer
4.0 Ordering Information
The AL440C has two speed grades, AL440C-20 and AL440C-12, which can operate at frequencies of 50MHz and 80MHz respectively. Both speed grades are powered by 3.3V and are available in a 44-pin standard TSOP-II package. Part number AL440C-20/12 (50/80MHz) Package PG44: 44-pin plastic TSOP(II) Power Supply +3.3V10% Status Sample 2004
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4.1 Marking Information
AL440x - xx
Speed Grade: XX = 20, 12 20: 50Mhz 12: 80Mhz Version Number: X = A, B, C..
xxxxx
Lot Number
xxxx
Date Code
5.0 Pin-out Diagram
The AL440C pin-out diagram is following.
GND /RESET RRST GND RCK VDD NC VDD DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 NC NC
24 21
44
43
42
41
40
39
38
37
36
35
OE
34
33
32
31
30
29
NC
28
27
26
25
AVERLOGIC
AL440C-20 XXXXX XXXX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22
WE
AVDD
DI0
WCK
DI1
DI2
DI3
DI4
DI5
DI6
DI7
GND
WRST
/PLRTY
AL440C-20/12 TSOP (II) pinout diagram (Top view)
AGND
TEST
VDD
IE
NC
NC
NC
NC
NC
23
RE
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AL440C
6.0 Block Diagram
DI[7:0]
Input Buffer
Write Data Register
Internal Bus
512kx8 memory cell array
Internal Bus
Read Data Register
Output Buffer
DO[7:0]
Memory Control WCK WRST IE WE Iutput Control Output Control Timing Generator & Arbiter RCK RRST OE RE
Address Bus
Control Bus
To all Modules
Refresh Counter Timing & Logic Control
/PLRTY /RESET
AL440C Block Diagram
The internal structure of AL440C consists of an Input/Output buffers, Write Data Registers, Read Data Registers and main 512k x8bit memory cell array and the state-of-the-art logic design that takes care of addressing and controlling the read/write data.
7.0 Pin Definition and Description
The pin definitions and descriptions are as follows:
Write Bus Signals
Pin name Pin number I/O type Description
DI[7:0]
9,8,7,6,4,3,2, 1 10 11
I
WE IE
I I
WCK WRST
13 14
I I
The DI pins input 8bits of data. Data input is synchronized with the WCK clock. Data is acquired at the rising edge of WCK clock. WE is an input signal that controls the 8bit input data write and write pointer operation. IE is an input signal that controls the enabling/ disabling of the 8bit data input pins. The internal write address pointer is always incremented at rising edge of WCK by enabling WE regardless of the IE level. WCK is the write clock input pin. The write data input is synchronized with this clock. The WRST is an input signal that resets the write address pointer to 0.
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*Note: For the polarity definition of all write control signals (WE, IE and WRST), please refer to /PLRTY pin definition and "Memory Operation" section for details.
Read Bus Signals
Pin name DO[7:0] Description Pin number I/O type 36,37,38,39, O The DO pins output 8bit of data. Data output is 41,42,43,44 synchronized with the RCK clock. Data is output at the rising edge of the RCK clock. 35 I RE is an input signal that controls the 8bit output data read and read pointer operation. 34 I OE is an input signal that controls the enabling/ disabling of the 8bit data output pins. The internal read address pointer is always incremented at rising edge of RCK by enabling RE regardless of the OE level. 32 I RCK is the read clock input pin. The read data output is synchronized with this clock. 31 I The RRST is an input signal that resets the read address pointer to 0.
RE OE
RCK RRST
*Note: For the polarity definition of all read control signals (RE, OE and RRST), please refer to /PLRTY pin definition and "Memory Operation" section for details.
Power/Ground Signals
Pin name VDD GND AVDD AGND Pin number I/O Description type 5, 29, 40 - 3.3V 10%. 12, 26, 33 - Ground. 18 - Dedicated power pin for the internal oscillator. 3.3V 10%. 22 - Dedicated ground pin for the internal oscillator.
Miscellaneous Signals
Pin name /RESET Pin number I/O Description type 27 I The global reset pin /RESET will automatically initialize chip logic and clear the window mode registers to 0. See Application note for the recommendation circuit of the global reset signal. Please refer to the Application Notes.
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/PLRTY
16
I
TEST NC
17 15, 19, 20, 21, 23~25, 28, 30
I -
Select active polarity of the control signals including WE, RE, WRST, RRST, IE and OE totally 6 signals /PLRTY = VDD, active low. /PLRTY = GND, active high. Note: During memory operation, the pin must be permanently connected to VDD or GND. The pin has internal Pull-High as default active low, if /PLRTY has no connection. If /PLRTY level is changed during memory operation, memory data is not guaranteed. For testing purpose only. Connect to Ground. No connect or connect to Ground
8.0 Multiple Devices Bus Expansion
The AL440C FIFO memory can be applied to very wide range of media applications. A parallel connect of multiple AL440C FIFOs provides extra FIFO bus width.
WRST DI[7:0] IE WE WCK
RRST DO[7:0] OE RE RCK
16-bit Input Bus Width
16-bit Output Bus Width
WRST DI[7:0] IE WE WCK
RRST DO[7:0] OE RE RCK
AL440C Data Bus Width Expansion
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9.0 Memory Operation
9.1 Power-On-Reset & Initialization
During the system power on, a 200s negative pulse on the /RESET pin is required and will automatically initialize chip logic and reset window mode registers to default value "0". Apply a valid reset pulse to WRST and RRST after power-on-reset to reset read/write address pointer to zero.
9.2 WRST, RRST Reset Operation
The reset signal can be given at any time regardless of the WE, RE and OE status, however, they still need to meet the setup time and hold time requirements with reference to the clock input. When the reset signal is provided during disabled cycles, the reset operation will not be executed until cycles are enabled again.
9.3 Control Signals Polarity Select
The AL440C provides the option for operating polarity on controlling signals. With this feature, the application design can benefit by matching up the operation polarity between AL440C and existing interfacing devices without additional glue logic. The operating polarity of control signals WE, RE, WRST, RRST, IE and OE are controlled by /PLRTY signal. When /PLRTY is pulled high all eight signals will be active low. When /PLRTY is pulled low all eight signals will be active high.
9.4 FIFO Write Operation
In the FIFO write operation, 8 bits of write data are input in synchronization with the WCK clock. The FIFO write operation is determined by WRST, WE, IE and WCK signals and the combination of these signals could produce different write result. The /PLRTY signal determines the activated polarity of these control signals. The following tables describe the WRITE functions under different operating polarities.
/PLRTY = VDD
WRST L H H WE L L IE L H WCK Function Write reset. The write pointer is reset to zero. Normal Write operation. Write address pointer increases, but no new data will be written to memory. Old data is retained in memory. (Write mask function) Write operation stopped. Write address pointer is also stopped.
H
H
-
/PLRTY = GND
WRST H L L WE H H IE H L WCK Function Write reset. The write pointer is reset to zero. Normal Write operation. Write address pointer increases, but no new data will be
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L
L
-
written to memory. Old data is retained in memory. (Write mask function) Write operation stopped. Write address pointer is also stopped.
9.5 FIFO Read Operation
In the FIFO read operation, 8 bits of read data are available in synchronization with the RCK clock. The access time is stipulated from the rising edge of the RCK clock. The FIFO read operation is determined by RRST, RE, OE and RCK signals, consequently the combination of these signals could produce varying read results. The /PLRTY signal could decide the activated polarity of these control signals. The following tables describe the READ functions under different operating polarities.
/PLRTY = VDD
RRST L L L RE L L H OE L H L RCK Function Read reset. The read pointer is reset to zero. Data in the address 0 is output. Read reset. The read pointer is reset to zero. Output is high impedance. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and data in the address 0 is output after RE goes low. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after RE goes low. Normal Read operation. Read address pointer increases. Output is high impedance. (Data skipping function) Read address pointer is stopped. Output data is held. Read operation stopped. Read address pointer is stopped. Output is high impedance.
L
H
H
H H H H
L L H H
L H L H
/PLRTY = GND
RRST H H H RE H H L OE H L H RCK Function Read reset. The read pointer is reset to zero. Data in the address 0 is output. Read reset. The read pointer is reset to zero. Output is high impedance. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and data in the address 0 is output after RE goes low. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after RE goes low. Normal Read operation.
H
L
L
L
H
H
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AL440C
L L L
H L L
L H L

Read address pointer increases. Output is high impedance. (Data skipping function) Read address pointer is stopped. Output data is held. Read operation stopped. Read address pointer is stopped. Output is high impedance.
When the new data is read, the read address should be between 192 and 524,287 cycles after the write address pointer, otherwise the output for new data is not guarantee.
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10.0 Electrical Characteristics
10.1 Absolute Maximum Ratings
Parameter VDD VP IO TAMB Tstg Supply Voltage Pin Voltage Output Current Ambient Op. Temperature Storage temperature Rating -0.3 ~ +3.8 -0.3 ~ +(VDD+0.3) -20 ~ +20 0 ~ +85 -40 ~ +125 Unit V V mA C C
10.2 Recommended Operating Conditions
Parameter VDD VIH VIL Supply Voltage High Level Input Voltage Low Level Input Voltage Min +3.16 0.7 VDD 0 Typ +3.3 Max +3.6 VDD 0.3 VDD Unit V V V
10.3 DC Characteristics
(VDD = 3.3V, Vss=0V. TAMB = 0 to 70C) Parameter ICC1 ISB1 ICC2 ISB2 VOH VOL ILI ILO RL
1. 2.
Min 2.4 -5 -5
Typ 88 113 50
Max VDD +0.4 +5 +5
Unit mA mA mA mA V V A A K
Operating Current Standby Current Operating Current Standby Current Hi-level Output Voltage Lo-level Output Voltage Input Leakage Current (No pull-up or pull-down) Output Leakage Current (No pull-up or pull-down) Input Pull-up/Pull-down Resistance
Tested with outputs disabled (IOUT = 0) RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
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10.4 AC Characteristics
(VDD = 3.3V, Vss=0V, TAMB = 0 to 70C)
Parameter TWC TWPH TWPL TRC TRPH TRPL TAC TOH THZ TLZ TWRS TWRH TRRS TRRH TDS TDH TWES TWEH TWPW TRES TREH TRPW TIES TIEH TIPW TOES TOEH TOPW WCK Cycle Time WCK High Pulse Width WCK Low Pulse Width RCK Cycle Time RCK High Pulse Width RCK Low Pulse Width Access Time Output Hold Time Output High-Z Setup Time Output Low-Z Setup Time WRST Setup Time WRST Hold Time RRST Setup Time RRST Hold Time Input Data Setup Time Input Data Hold Time WE Setup Time WE Hold Time WE Pulse Width RE Setup Time RE Hold Time RE Pulse Width IE Setup Time IE Hold Time IE Pulse Width OE Setup Time OE Hold Time OE Pulse Width 20 7 7 20 7 7 4 3 3 5 2 5 2 5 2 5 2 10 5 2 10 5 2 10 5 2 10
50MHz Min Max 15 15 15 -
80MHz Min 12.5 5 5 12.5 5 5 4 4 5 4 5 4 5 4 5 4 5 12 4 5 12 4 5 12 5 5 12 Max 12 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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AL440C
TTR CI CO
Transition Time Input Capacitance Output Capacitance
2 -
20 7 7
3 -
7 7
ns pF pF
*
The read address needs to be at least 192 cycles after the write address.
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AL440C
11.0 Timing Diagrams
cycle n
Reset cycle (s)
cycle 0
cycle 1
WCK
TTR TWRS TWRH
WRST
TDS
TDH
DI7~0
n-1
n
0
1
/PLRTY=VDD
, WE= "L"
, IE= "L"
Write Cycle Timing (Write Reset)
cycle n TWPL
cycle n+1
Disable cycle (s)
cycle n+2
WCK
TWPH TWC TWES TWEH
WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
n+2
/PLRTY=VDD ,IE="L"
,WRST="H" Write Cycle Timing (Write Enable)
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AL440C
cycle n TWPL
cycle n+1
Disable cycle (s)
cycle 0
cycle 1
WCK
TWPH
TWC
TWRS
TWRH
WRST
TWES
TWEH
WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
0
1
/PLRTY=VDD ,IE="L" Write Cycle Timing (WE, WRST)
cycle n TWPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
WCK
TWPH TWC TIES TIEH
IE
TIPW
TIH
DI7~0
n-1
n
n+1
n+4
/PLRTY=VDD ,WE="L"
,WRST="H" Write Cycle Timing (Input Enable)
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cycle n TRPL Reset cycle (s) cycle 0 cycle 1
RCK
TRPH
TRRS
TRRH
RRST
TAC TOH
DO7~0
n-1
n
0
0
1
/PLRTY=VDD
,RE= "L"
,OE= "L"
Read Cycle Timing (Read Reset)
cycle n TRPL
cycle n+1
Disable cycle (s)
cycle n+2
RCK
TRPH TRC TRES TREH
RE
TRPW TAC TOH
DO7~0
n-1
n
n+1
n+2
/PLRTY=VDD ,OE="L" ,RRST="H" Read Cycle Timing (Read Enable)
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cycle n TRPL
cycle n+1
Disable cycle (s)
cycle 0
RCK
TRPH TRC TRRS TRRH
RRST
TRES
TREH
RE
TRPW TAC TOH
DO7~0
n-1
n
n+1
0
/PLRTY=VDD ,OE="L" Read Cycle Timing (RE, RRST)
cycle n TRPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
RCK
TRPH TRC TOES TOEH
OE
TOPW TAC TOH THZ Hi-Z TLZ
DO7~0
n-1
n
n+1
n+4
/PLRTY=VDD ,RE="L"
,RRST="H" Read Cycle Timing (Output Enable)
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cycle n
Reset cycle (s)
cycle 0
cycle 1
WCK
TTR TWRS TWRH
WRST
TDS
TDH
DI7~0
n-1
n
0
1
/PLRTY=GND
, WE= "H"
, IE= "H"
Write Cycle Timing (Write Reset)
cycle n TWPL
cycle n+1
Disable cycle (s)
cycle n+2
WCK
TWPH TWC TWES TWEH
WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
n+2
/PLRTY=GND ,IE="H"
,WRST="L" Write Cycle Timing (Write Enable)
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cycle n TWPL
cycle n+1
Disable cycle (s)
cycle 0
cycle 1
WCK
TWPH
TWC
TWRS
TWRH
WRST
TWES
TWEH
WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
0
1
/PLRTY=GND ,IE="H" Write Cycle Timing (WE, WRST)
cycle n TWPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
WCK
TWPH TWC TIES TIEH
IE
TIPW
TIH
DI7~0
n-1
n
n+1
n+4
/PLRTY=GND ,WE="H"
,WRST="L" Write Cycle Timing (Input Enable)
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cycle n TRPL Reset cycle (s) cycle 0 cycle 1
RCK
TRPH
TRRS
TRRH
RRST
TAC TOH
DO7~0
n-1
n
0
0
1
/PLRTY=GND ,RE= "H"
,OE= "H"
Read Cycle Timing (Read Reset)
cycle n TRPL
cycle n+1
Disable cycle (s)
cycle n+2
RCK
TRPH TRC TRES TREH
RE
TRPW TAC TOH
DO7~0
n-1
n
n+1
n+2
/PLRTY=GND ,OE="H"
,RRST="L" Read Cycle Timing (Read Enable)
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cycle n TRPL
cycle n+1
Disable cycle (s)
cycle 0
RCK
TRPH TRC TRRS TRRH
RRST
TRES
TREH
RE
TRPW TAC TOH
DO7~0
n-1
n
n+1
0
/PLRTY=GND ,OE="H" Read Cycle Timing (RE, RRST)
cycle n TRPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
RCK
TRPH TRC TOES TOEH
OE
TOPW TAC TOH THZ Hi-Z TLZ
DO7~0
n-1
n
n+1
n+4
/PLRTY=GND
,RE="H"
,RRST="L" Read Cycle Timing (Output Enable)
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12.0 Mechanical Drawing - 44 PIN PLASTIC TSOP (II)
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"D "
(Unit: mm)
"E1"
"b"
NOTE: 1. Controlling Dimension: Millimeters. 2. Dimension "D" does not include mold protrusion. Mold protrusion shall not exceed 0.15(0.006") per side. Dimension "E1" does not include interlead protrusion. Interlead protrusion shall not exceed 0.25(0.01") per side. 3. Dimension "b" does not include damar protrusions/intrusion. Allowable damar protrusion shall not cause the lead to be wider than the MAX "b" dimension by more than 0.13mm. Damar intrusion shall not cause the lead to be narrower than the MIN "b" dimension by more than 0.07mm.
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13.0 Application Notes
13.1 Chip Global Reset Recommend Circuit
To ensure a proper reset pulse can be applied to /RESET pin (pin 27) to complete the power-on reset, the recommend reset circuit is to connect the AL440C /RESET pin (pin 27) to VDD with a 2k resistor and to Ground with a 10f capacitor as follows.
AL440C
8-bit Input DI[7:0] DO[7:0] 8-bit Output
VDD 2K Ohm
27
/RESET
50K Ohm
10 uf
AL440C Global Reset Circuit
It is also recommend adding buffers for the power-on reset circuit to increase the driving capability for any application with multiple AL440C chips.
13.2 The AL440C Reference Schematic
U8 AL440 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 RNSMD1 1 2 3 4 10 8 7 6 5 CTL0 CTL1 CTL2 CTL3 10 11 13 14 15 CTL5 16 17 WE IE WCK WRST I PLRTY TEST RE OE RCK RRST 35 34 32 31 30 1 2 3 4 6 7 8 9 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 44 43 42 41 39 38 37 36 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 RNSMD3 CTL7 1 CTL8 2 CTL9 3 CTL10 4 10 8 7 6 5 8 RE OE RCK RRST
WE IE WCK WRST
R2 VDD3S
2K
R3
2K RNSMD4 5 29 40 VDD VDD VDD /RESET AVDD 27 18 FAVDD 0.1uf 12 26 33 GND GND GND AGND NC NC NC NC 22 C62 R5 1 10 2 VDD3S + C67 10uF 10 R1 2K VDD3S
Populate R2 or R3 to select Control Signals polarity
VDD3S 1 L5 F B FB 2 0.1uf C55 10uF FDVDD 0.1uf 0.1uf C56 C57
F L7
B FB
C54 +
28 19 20 21
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CONTACT INFORMATION
AverLogic Technologies, Inc. 90 Great Oaks Blvd. #204 San Jose, CA 95119 USA Tel : +1 408 361-0400 Fax : +1 408 361-0404 E-mail : sales@averlogic.com URL : www.averlogic.com
AverLogic Technologies, Corp. 4F., No.514, Sec.2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan R.O.C Tel : +886 2-27915050 Fax : +886 2-27912132 E-mail : sales@averlogic.com.tw URL : www.averlogic.com.tw

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